/*
 * (C) Copyright 2007-2013
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Jerry Wang <wangflord@allwinnertech.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef  __dram_head_h__
#define  __dram_head_h__

typedef struct __DRAM_PARA
{
    //normal configuration
    unsigned int        dram_clk;
    unsigned int        dram_type;      //dram_type DDR2:2 DDR3:3 LPDDR2:6 LPDDR3:7  DDR3L:31
    //unsigned int        lpddr2_type;  //LPDDR2 type S4:0  S2:1 NVM:2
    unsigned int        dram_zq;        //do not need
    unsigned int        dram_odt_en;

    //control configuration
    unsigned int        dram_para1;
    unsigned int        dram_para2;

    //timing configuration
    unsigned int        dram_mr0;
    unsigned int        dram_mr1;
    unsigned int        dram_mr2;
    unsigned int        dram_mr3;
    unsigned int        dram_tpr0;  //DRAMTMG0
    unsigned int        dram_tpr1;  //DRAMTMG1
    unsigned int        dram_tpr2;  //DRAMTMG2
    unsigned int        dram_tpr3;  //DRAMTMG3
    unsigned int        dram_tpr4;  //DRAMTMG4
    unsigned int        dram_tpr5;  //DRAMTMG5
    unsigned int        dram_tpr6;  //DRAMTMG8

    //reserved for future use
    unsigned int        dram_tpr7;
    unsigned int        dram_tpr8;
    unsigned int        dram_tpr9;
    unsigned int        dram_tpr10;
    unsigned int        dram_tpr11;
    unsigned int        dram_tpr12;
    unsigned int        dram_tpr13;


}__dram_para_t;

#ifdef FPGA_PLATFORM
unsigned int mctl_init(void *para);
#else
extern int init_DRAM( int type, __dram_para_t *buff );
extern void dram_enable_all_master(void);
extern void dram_disable_all_master(void);
#endif
#endif
